industrial temperature range idt5t9050 2.5v single data rate 1:5 clock buffer terabuffer jr. 1 october 2002 idt5t9050 industrial temperature range 2.5v single data rate 1:5 clock buffer terabuffer? jr. description: the idt5t9050 2.5v single data rate (sdr) clock buffer is a single-ended input to five single-ended outputs buffer built on advanced metal cmos technology. the sdr clock buffer fanout from a single input to five single-ended outputs reduces the loading on the preceding driver and provides an efficient clock distribution network. multiple power and grounds reduce noise. the idt logo is a registered trademark of integrated device technology, inc. ? 2002 integrated device technology, inc. dsc-5958/18 features: ? optimized for 2.5v lvttl ? guaranteed low skew < 25ps (max) ? very low duty cycle distortion < 300 (max) ? high speed propagation delay < 1.8ns. (max) ? up to 200mhz operation ? very low cmos power levels ? hot insertable and over-voltage tolerant inputs ? 1:5 fanout buffer ? 2.5v v dd ? available in tssop package functional block diagram applications: ? clock and signal distribution gl g a output control output control output control output control output control q 1 q 2 q 3 q 4 q 5
industrial temperature range 2 idt5t9050 2.5v single data rate 1:5 clock buffer terabuffer jr. tssop top view pin configuration gl gnd v dd v dd gnd gnd gnd g v dd v dd q 1 q 2 q 5 gnd gnd q 3 a q 4 v dd v dd gnd gnd gnd v dd v dd v dd nc nc 19 15 16 17 18 20 21 22 23 24 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 symbol description max unit v dd power supply voltage ?0.5 to +3.6 v v i input voltage ?0.5 to +3.6 v v o output voltage ?0.5 to v dd +0.5 v t stg storage temperature ?65 to +165 c t j junction temperature 150 c absolute maximum ratings (1) note: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. symbol parameter min typ. max. unit c in input capacitance ? 6 ? pf capacitance (1) (t a = +25c, f = 1.0mhz) note: 1. this parameter is measured at characterization but not tested. symbol description min. typ. max. unit t a ambient operating temperature ?40 +25 +85 c v dd internal power supply voltage 2.3 2.5 2.7 v recommended operating range pin description symbol i/o type description a i lvttl clock input g i lvttl gate control for qn outputs. when g is low, these outputs are enabled. when g is high, these outputs are asynchronously disabled to the level designated by gl (1) . gl i lvttl specifies output disable level. if high, the outputs disable high. if low, the outputs disable low. qn o lvttl clock outputs v dd pwr power supply for the device core, inputs, and outputs gnd pwr power supply return for power note: 1. because the gate controls are asynchronous, runt pulses are possible. it is the user's responsibility to either time the gat e control signals to minimize the possibility of runt pulses or be able to tolerate them in down stream circuitry.
industrial temperature range idt5t9050 2.5v single data rate 1:5 clock buffer terabuffer jr. 3 notes: 1. see recommended operating range table. 2. voltage required to maintain a logic high. 3. voltage required to maintain a logic low. 4. typical values are at v dd = 2.5v, +25c ambient. dc electrical characteristics over operating range (1) symbol parameter test conditions min. typ. (4) max unit i ih input high current v dd = 2.7v v i = v dd /gnd ? ? 5 a i il input low current v dd = 2.7v v i = gnd/v dd ??5 v ik clamp diode voltage v dd = 2.3v, i in = -18ma ? - 0.7 - 1.2 v v in dc input voltage - 0.3 +3.6 v v ih dc input high (2) 1.7 ? v v il dc input low (3) ? 0.7 v v oh output high voltage i oh = -12ma v dd - 0.4 ? v i oh = -100 av dd - 0.1 ? v v ol output low voltage i ol = 12ma ? 0.4 v i ol = 100 a ? 0.1 v input ac test conditions symbol parameter value units v ih input high voltage v dd v v il input low voltage 0v v th input timing measurement reference level (1) v dd /2 v t r , t f input signal edge rate (2) 2 v/ns notes: 1. a nominal 1.25v timing measurement reference level is specified to allow constant, repeatable results in an automatic test eq uipment (ate) environment. 2. the input signal edge rate of 2v/ns or greater is to be maintained in the 10% to 90% range of the input waveform. power supply characteristics symbol parameter test conditions (1) typ. max unit i ddq quiescent v dd power supply current v dd = max., reference clock = low 1 1.5 ma outputs enabled, all outputs unloaded i ddd dynamic v dd power supply v dd = max., c l = 0pf 100 150 a/mhz current per output i tot total power v dd supply current v dd = 2.5v., f reference clock = 100mhz, c l = 15pf 50 65 ma v dd = 2.5v., f reference clock = 200mhz, c l = 15pf 75 100 note: 1. the termination resistors are excluded from these measurements.
industrial temperature range 4 idt5t9050 2.5v single data rate 1:5 clock buffer terabuffer jr. ac electrical characteristics over operating range (4) symbol parameter min. typ. max unit skew parameters t sk ( o ) same device output pin-to-pin skew (1) ?? 25 ps t sk ( p ) pulse skew (2) ?? 300 ps t sk ( pp ) part-to-part skew (3) ?? 300 ps propagation delay t plh propagation delay a to qn ?? 1.8 ns t phl t r output rise time (20% to 80%) 350 ? 850 ps t f output fall time (20% to 80%) 350 ? 850 ps f o frequency range ?? 200 mhz output gate enable/disable delay t pge output gate enable to qn ?? 3.5 ns t pgd output gate enable to qn driven to gl designated level ?? 3ns notes: 1. skew measured between all outputs under identical input and output transitions and load conditions on any one device. 2. skew measured is the difference between propagation delay times t phl and t plh of any output under identical input and output transitions and load conditions on any one device. 3. skew measured is the magnitude of the difference in propagation times between any outputs of two devices, given identical tra nsitions and load conditions at identical v dd levels and temperature. 4. guaranteed by design. propagation and skew waveforms note: pulse skew is calculated using the following expression: t sk ( p ) = | t phl - t plh | where t phl and t plh are measured on the controlled edges of any one output from rising and falling edges of a single pulse. please note that the t phl and t plh shown are not valid measurements for this calculation because they are not taken from the same pulse. ac timing waveforms t plh t phl t sk(o) t sk(o) qn qm v oh v th v ol v oh v th v ol a v ih v th v il t w t w 1/fo
industrial temperature range idt5t9050 2.5v single data rate 1:5 clock buffer terabuffer jr. 5 note: as shown, it is possible to generate runt pulses on gate disable and enable of the outputs. it is the user's responsibility to time their g signal to avoid this problem. t plh gl g qn v ih v th v il v ih v th v il v oh v th v ol t pgd t pge a v ih v th v il gate disable/enable showing runt pulse generation
industrial temperature range 6 idt5t9050 2.5v single data rate 1:5 clock buffer terabuffer jr. test circuit for input/output input/output test conditions symbol v dd = 2.5v 0.2v unit v th v dd / 2 v r1 100 ? r2 100 ? c l 15 pf v dd d.u.t. c l v dd r1 r2 qn a pulse generator v in 3 inch, ~50 ? transmission line v dd r1 r2 test circuit and conditions
industrial temperature range idt5t9050 2.5v single data rate 1:5 clock buffer terabuffer jr. 7 ordering information idt xxxxx package device type 5t9050 2.5v single data rate 1:5 clock buffer terabuffer jr. thin shrink small outline package tssop - green pg pgg xx package x -40c to +85c (industrial) i corporate headquarters for sales: for tech support: 2975 stender way 800-345-7015 or 408-727-6116 logichelp@idt.com santa clara, ca 95054 fax: 408-492-8674 (408) 654-6459 www.idt.com
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